Programme of DCC'08 at ETAPS 2008

(Designing Correct Circuits 2008)

29th March 2008, room: Margit

09:00 - 10:30 SESSION 1

Model Checking Transactional memory
John O'Leary, Bratin Saha, Mark R. Tuttle (Strategic CAD Labs, Intel Corporation)
Formally Verifying Handel-C Hardware Synthesis
Juan Ignacio Perna, Jim Woodcock (University of York)

10:30 - 11:00 Coffee

11:00 - 12:30 SESSION 2

Obsidian: An Embedded Language for Data-Parallel Programming
Joel Svensson, Koen Claessen, Mary Sheeran (Chalmers University)
Describing Hardware with Parallel Programs
David Greaves (University of Cambridge), Satnam Singh (Microsoft Research, Cambridge)

12:30 - 14:00 Lunch

14:00 - 16:00 SESSION 3

Accessing Circuit Generators in Embedded HDLs
Gordon Pace, Christian Tabone (University of Malta)
Flexible Hardware Design at Low Levels of Abstraction
Emil Axelsson (Chalmers University)

16:00 - 16:30 Coffee

30th March 2008, room: Margit changed to Room III.

09:00 - 10:30 SESSION 1

Design and Verification of On-Chip Communication Protocols
Peter Bohm, Tom Melham (University of Oxford)
Parametric Verification of Industrial Cache Protocols
Murali Talupur, Sava Krstic, John O'Leary, Mark R. Tuttle (Strategic CAD Labs, Intel Corporation)

10:30 - 11:00 Coffee

11:00 - 12:30 SESSION 2

Defining Elastic Circuits with Negative Delays
Sava Krstic (Strategic CAD Labs, Intel), Jordi Cortadella (Univesitat Politčica de Catalunya, Barcelona), Mike Kishinevsky (Strategic CAD Labs, Intel), John O'Leary (Strategic CAD Labs, Intel)
Some "Real World" Problems in the Analog and Mixed Signal Domains
Kevin Jones, Jaeha Kim, Victor Konrad (Rambus Inc)

12:30 - 14:00 Lunch

14:00 - 16:00 SESSION 3

Efficient Circuit Design with uDL
Steve Hoover (Massachusetts Microprocessor Design Center, Intel)
Bridging the Gap between Abstract RTL and Bit-Level Designs
Andrew K. Martin (IBM)

16:00 - 16:30 Coffee

Detailed Programme Information:

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